The present invention relates to a semiconductor integrated circuit device fabrication technique and a semiconductor integrated circuit device obtained by the technique, and particularly to a technique for connecting a semiconductor chip to a printed wiring board by face down bonding of a semiconductor chip to a wiring substrate using metallic bumps.
The flip chip method has been known as an electrode connection technique for a semiconductor chip having many input/output terminals such as a gate array or a microcomputer. A known typical flip chip method is the CCB (Controlled Collapse Bonding) method for forming spherical bump electrode (CCB bump) made of solder on the electrode pads of a semiconductor chip to connect the semiconductor chip to a printed wiring board by using CCB bumps. The CCB method allows electrodes to be formed not only at the marginal part of a semiconductor chip, but also at the central portion thereof, producing a semiconductor device having multi-pin formation with decrease in the wiring lengths of the semiconductor device in comparison to the wire bonding method. A semiconductor device formed using the CCB method therefore provides a faster operating speed due to the shorter wiring length.
The CCB bumps are typically formed on the electrode pads of a semiconductor chip by a solder vacuum or evaporation deposition technique. To form the CCB bumps by using this technique, metal thin film layers (BLM: Ball Limiting Metallization) of Cr, Cr/Cu, Cu and Au or the like are vacuum-deposited on the semiconductor electrode pads. The solder has tendency to diffuse during the CCB bump formation due to the thermal hysteresis. The BLM layers prevent the solder from diffusing during the CCB bump formation. Then, a thin film layer of solder (Sn/Pb alloy) is deposited over the semiconductor chip surface, including over the BLM layers. The solder film layer is removed in areas other than the above portion of the BLM layer using a lifted off technique. When the solder thin film left on the BLM layers is melted, the surface tension creates a ball-shaped CCB bump on the electrode pad. The semiconductor chip and the wiring substrate are electrically connected through the CCB bumps by aligning the semiconductor chip over the electrode pads or the wiring lands on the wiring substrate and then remelting (reflow). Then, the semiconductor chip connected to the printed wiring board is hermetically sealed by a cap or the like.
The CCB bump forming technique is described in detail, for example, in the Journal of the Institute of Metal Engineers of Japan, Vol. 23, No. 12 (1984), pp. 1004-1013 and Data for Symposium of the Institute of Electrical Engineers of Japan, published on Mar. 17, 1989, p. 45-47. Also regarding an LSI package where a semiconductor chip mounted on a wiring substrate by the CCB system is hermetically sealed by a cap, description is found, for example, in JPA No. 249429/1987 or JPA No. 310139/1988.
Techniques have been recently studied to connect a GaAs chip having a high-speed IC operated on radio frequencies of 10 GHz or higher to a printed wiring board by using a flip chip method. However, in the CCB method for connecting a semiconductor chip to a printed wiring board by heating and reflowing CCB bumps, it is necessary to form internal layer wirings on the printed wiring board, taking the solder flow and the CCB bump shape control in consideration. A problem has been found in that transmission loss of high-frequency signals is produced due to the through-holes necessary to form internal layer wirings. In order to overcome this problem, a ceramic thick film board on which wiring and wiring lands are formed by a printing method is used. However, another problem arises in using the ceramic film board in that the reliability of connection between CCB bumps and wiring lands is low because the ceramic thick film board has large positional deviation of the wiring lands due to the misregistration and bleeding during printing and the shrinkage tolerance of ceramic during baking.
Moreover, the ceramic film board with the CCB bumps poses many disadvantages in that 1) it has a low reliability of connection between CCB bumps and wiring lands because the board largely warps and waves relative to a semiconductor chip; 2) the wiring lands further have variations in film thickness and thus uneven heights; 3) it is difficult to conduct the heat generated by a semiconductor chip to the printed wiring board through CCB bumps because solder which is the material of the CCB bumps has a large thermal resistance; 4) a CCB bump has a short service life because it is made of solder (Pb--Sn alloy) which easily causes thermal fatigue failure; and 5) the fabrication cost is high because an expensive vacuum deposition equipment and a complex lift-off process are necessary to form the CCB bumps and BLM layers.